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- 1 - ts 52001 version 1. 3 specifications subject to change www.triunesystems.com copyright ? 2011 , triune systems, llc description features ? utilizes a temperature - independent pv mppt - lite? regulation scheme ? v ba t reverse current blocking ? programmable temperature - compensated termination voltage with +/ - 1% tolerance ? up to 1.5a of continuou s output current in full charge constant - current (cc) mode ? user programmable charging current ? high efficiency C up to 92% at typical load ? current mode pwm control in constant voltage ? supervisor for v bat reported at the nflt pin ? input supply under - voltage l ockout ? full protection for v bat over - current, over - temp, over - voltage, and charging timeout ? charge status indication ? i2c program interface with eep rom registers summary specifications ? wide input voltage range: 4.0v to 8.1 v ? packaged in a 16pin qfn (4x4) typical application the TS52001 is a dc/dc synchronous switching li - ion battery charger with fully integrated power switch es, internal compensation, and full fault protection. the TS52001 utilizes a temperature - independent photovoltaic maximum power point tracking (mppt - l ite? ) calculator to optimize power output from the source during full charge constant - current (cc) mode. the switching frequency of 1mhz enables the use of small filter components, resulting in smaller board space and reduced bom costs. in full charge c onstant - current mode the duty cycle is controlled by the mppt - lite? regulator. once termination voltage is reached, the regulator operates in voltage mode. when the regulator is disabled (en is low), the device draws 1 0 ua quiescent current. the TS52001 includes supervisory reporting through the nflt (inverted fault) open drain output to interface other components in the system. device programming is achieved by an i2c interface through scl and sda pins. applications ? portable solar chargers ? off - grid s ystems ? wireless sensor networks ? smoke detectors ? hvac controls high efficiency li - ion battery charger for photovoltaic sources nflt TS52001 g n d e n v t h e r m s w p g v b a t s c l p g n d c o u t l o u t r s e n s e r r e f v i n s d a v t h _ r e f p h o t o v o l t a i c c e l l s v s e n s e b a t t e r y r t h m r p u l l u p ( o p t i o n a l ) v d d r p u l l u p ( o p t i o n a l ) v d d c i n v d d c v d d
- 2 - ts 52001 version 1. 3 specifications subject to change www.triunesystems.com copyright ? 201 1 , triune systems, llc pinout figure 1b: package pinout diagram pin description pin symbol pin # function description sw 1 switching voltage node connected to 4.7uh (typical) inductor v in 2 photovoltaic input voltage input voltage v sense 3 current sense positive input positive input for the mpp current loop. vbat 4 battery input regulator feedback input gnd 5 gnd primary ground for the majority of the device except the low - side powe r fet. en 6 enable input above 2.2v the device is enabled. gnd the pin to disable the device. includes internal pull - up. nflt 7 inverted fault open - drain output. vdd 8 internal 3.3v supply output connected to 100nf capacitor to gnd vtherm 9 battery t emperature sensor minus node minus node for the thermistor which is located in close proximity to the battery. vth_ref 10 battery temperature sensor positive node positive node for the thermistor which is located in close proximity to the battery vin 11 photovoltaic input voltage input voltage scl 12 clock input i 2 c clock input. sda 13 data input/output i 2 c data open - drain output. sw 14 switching voltage node connected to 4.7uh (typical) inductor pgnd 15 power gnd gnd supply for internal low - side fet /integrated diode pgnd 16 power gnd gnd supply for internal low - side fet/integrated diode TS52001 t s 5 2 0 1 q f n 1 6 4 x 4 t o p / s y m b o l i z a t i o n v i e w v i n v s e n s e v b a t s w v i n v t h _ r e f v t h e r m s c l s w p g n d p g n d s d a n f l t e n g n d v d d
- 3 - ts 52001 version 1. 3 specifications subject to change www.triunesystems.com copyright ? 201 1 , triune systems, llc functional block dia gram figure 2 : ts52 0 01 block diagram v i n b a t t c u r r e n t c o n t r o l g a t e d r i v e g a t e d r i v e g a t e d r i v e c o n t r o l v b a t s w o s c i l l a t o r r a m p g e n e r a t o r c o m p a r a t o r e r r o r a m p g n d m o n i t o r & c o n t r o l b a t t t h e r m a l c o n t r o l o v e r v o l t a g e p r o t e c t i o n v b a t v i n v i n ? e n p g n d n f l t c o u t l o u t b a t t c o m p e n s a t i o n n e t w o r k b a c k g a t e b l o c k i n g v t h _ r e f v t h e r m p h o t o v o l t a i c c e l l s ~ 5 v @ 4 5 0 m a v r e f v b a t r t h m r r e f r s e n s e v s e n s e m p p & c u r r e n t c o n t r o l i 2 c i n t e r f a c e s c l s d a v i n c i n v d d c v d d v d d r e g u l a t o r v i n
- 4 - ts 52001 version 1. 3 specifications subject to change www.triunesystems.com copyright ? 201 1 , triune systems, llc absolute maximum rat ings over operating free C air temperature rang e unless otherwise noted (1,2 ,3 ) parameter range unit vin, en , nflt , scl, sda, vtherm, vth_ref , vbat, vsense - 0.3 to 8 .8 v sw - 1 to 8.8 v vdd - 0.3 to 3.6 v operating junction temperature range, t j - 40 to 125 ? c storage temperature range, t s tg - 65 to 150 ? c electrostatic discharge C human body model 2k v electrostatic discharge C machine model +/ - 200 v lead temperature (soldering, 10 seconds) 260 ? c (1) stresses beyond those listed under absolute maximum ratings may cause permanent dam age to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is n ot implied. exposure to absolute C maximum C rated conditions for exte nded periods may affect device reliability. (2) all voltage values are with respect to network ground terminal. (3) esd testing is performed according to the respective jesd22 jedec standard. thermal characterist ics symbol parameter value unit ? ja t hermal resistance junction to air (note 1) 50 c/w note 1: assumes 4x4 qfn - 16 in 1 in 2 area of 2 oz copper and 25 ? c ambient temperature. recommended operatin g conditions symbol parameter min typ max unit vin photovoltaic input operating voltage 4 8.1 v r sense sense resistor 50 m ? l out output filter inductor typical value (note 1) 4.7 uh c out output filter capacitor typical value (note 2) 4.7 uf c out - esr output filter capacitor esr 100 m ? c in input supply bypass capacitor value (note 3) 3. 3 10 uf c vdd vdd supply bypass capacitor value (note 2) 70 100 130 nf t a operating free air temperature - 40 85 ? c t j operating junction temperature - 40 125 ? c note 1: for best performance, an inductor with a saturation current rating higher than t he maximum v ba t load requirement plus the inductor current ripple. note 2: for best performance, a low esr ceramic capacitor should be used. note 3: for best performance, a low esr ceramic capacitor should be used. if c in is not a low esr ceramic capacito r, a 0.1uf ceramic capacitor should be added in parallel to c in .
- 5 - ts 52001 version 1. 3 specifications subject to change www.triunesystems.com copyright ? 201 1 , triune systems, llc characteristics electrical characteristics, t j = - 40c to 125c, vin = 5.3v (unless otherwise noted) symbol parameter condition min typ max unit vin supply voltage vin photovoltaic voltag e input 4 8.1 v i cc - norm quiescent current normal mode i load = 0a , no switching 3 ma i cc - disable quiescent current disable mode en = 0v 1 0 50 ua vbat leakage i bat - leak leakage current from batt en = 0v , v bat = 4.1v 10 ua i bat - back reverse curr ent v bat > vin , v bat = 4.1v , tj < 85c 10 ua vin under - voltage lockout vin - uv input supply under - voltage threshold vin increasing 3.15 v vin - uv_hyst input supply under - voltage threshold hysteresis 100 200 mv osc f osc oscillator frequency 0.9 1 1.1 mhz nflt open drain output i oh - nflt high - level output leakage v nflt = 5.3v 0.1 ua v ol - nflt low - level output voltage i nflt = - 1ma 0.4 v en/scl/sda input voltage thresholds v ih high level input voltage 2.2 v v il low level input voltage 0.8 v v hyst input hysteresis 200 mv i in - en input leakage v en =vin 0.1 ua v en =0v - 2.0 ua i in - scl input leakage v scl =vin 55 ua v scl =0v - 0.1 ua i in - sda input leakage v sda =vin 0.1 ua v sda =0v - 0.1 ua v ol - sda low - level output volta ge i sda = - 1ma 0.4 v thermal shutdown tsd thermal shutdown junction temperature 150 170 c tsd hyst tsd hysteresis 10 c pre - charge end v prechg pre - charge voltage threshold 2.9 3.0 3.1 v vpc hyst pre - charge voltage hysteresis 70 mv char ge restart v restart voltage below termination for charging restart 10 0 mv
- 6 - ts 52001 version 1. 3 specifications subject to change www.triunesystems.com copyright ? 201 1 , triune systems, llc charger characterist ics electrical characteristics, t j = - 40c to 125c, vin = 5.3v (unless otherwise noted) symbol parameter condition min typ max unit charging regulato r: l=4.7uh and c=4.7uf i ba t - fc output current limit in full - charge mode i ba t = 1 .5 a i ba t - 10 % i ba t i ba t + 10 % a v ba t - to termination voltage in top - off mode i bat = 0.1c , 0c < tj < 85c v ba t - 1% v ba t v ba t + 1% v t to top - off mode time out 0 120 min t fc full - charge timer 20 0 1400 m in t acc timer accuracy - 10% +10% r dson high side switch on resistance i sw = - 1a, t j =25c 20 0 m? sw = 1a, t j =25c 2 50 m? bat max output current 1.5 a i ocd over - current detec t hs switch current 2.5 a v ba t - ov v ba t over - voltage threshold 101% v ba t 102% v ba t 103% v ba t duty max max duty cycle 9 8 % i 2 c interface timing r equirements electrical characteristics, t j = - 40c to 125c, vin = 5.3v (unless otherwise noted) symbol parameter standard mode fast mode (1) unit min max min max f scl i 2 c clock frequency 0 100 0 400 khz t sch i 2 c clock high time 4 0.6 s t scl i 2 c clock low time 4.7 1.3 s t sp (2) i 2 c tolerable spike time 0 50 0 50 ns t sds i 2 c serial data setup ti me 250 25 0 ns t sdh i 2 c serial data hold time 0 0 s t icr (2) i 2 c input rise time 1000 300 ns t icf (2) i 2 c input fall time 300 300 ns t ocf (2) i 2 c output fall time; 10 pf to 400 pf bus 300 300 n s t buf i 2 c bus free time between stop and start 4.7 1.3 s t sts i 2 c start or repeated start condition setup time 4.7 0.6 s t sth i 2 c start or repeated start condition hold time 4 0.6 s t sps (2) i 2 c stop condition setup time 4 0.6 s (1) the i2c interface will operate in either standard or fast mode . (2) parameters not tested in production .
- 7 - ts 52001 version 1. 3 specifications subject to change www.triunesystems.com copyright ? 201 1 , triune systems, llc thermistor character istics electrical characteristics, t j = - 40c to 125c, vin = 5.3v (unless otherwise noted) symbol parameter condition min typ max unit v vt h _ref vt h _ref output voltage i vt_ref = 2ua - 100ua 1.22 v 10 k? temperature thresholds C =3434k 0c 0c vtherm threshold (0c) decreasing temperature 75.6 %vth _ref 0c hyst 0c vtherm threshold with hysteresis (10c) increasing temperature 66.5 %vth _ref 10c 10c vtherm threshold (10c) decreasing temperature 66.2 %vth _ref 10c hyst 10c vtherm threshold with hysteresis (11c) increasing temperature 65.4 %vth _ref 45c 45c vtherm threshold (45c) increasing temperature 34.5 %vth _ref 45c hyst 45c vtherm threshold with hysteresis (44c) decreasing tempe rature 35.3 %vth _ref 50c 50c vtherm threshold (50c) increasing temperature 30.8 %vth _ref 50c hyst 50c vtherm threshold with hysteresis (49c) decreasing temperature 31.5 %vth _ref 60c 60c vtherm threshold (60c) increasing temperature 24.9 %vth _ref 60c hyst 60c vtherm threshold with hysteresis (50c) decreasing temperature 30.8 %vth _ref 100k? temperature thresholds C =4311k 0c hyst 0c vtherm threshold with hystere sis (10c) increasing temperature 69.8 %vth _ref 10c 10c vtherm threshold (10c) decreasing temperature 69.8 %vth _ref 10c hyst 10c vtherm threshold with hysteresis (11c) increasing temperature 68.6 %vth _ref 45c 45c vtherm threshold (45c) inc reasing temperature 31.3 %vth _ref 45c hyst 45c vtherm threshold with hysteresis (44c) decreasing temperature 32.3 %vth _ref 50c 50c vtherm threshold (50c) increasing temperature 27.0 %vth _ref 50c hyst 50c vtherm threshold with hysteresis (49 c) decreasing temperature 27.8 %vth _ref 60c 60c vtherm threshold (60c) increasing temperature 19.4 %vth _ref 60c hyst 60c vtherm threshold with hysteresis (50c) decreasing temperature 27.0 %vth _ref
- 8 - ts 52001 version 1. 3 specifications subject to change www.triunesystems.com copyright ? 201 1 , triune systems, llc functional description the ts52 0 01 is a fully - integrated li - ion battery charger ic based on a highly - efficient switching topology. it includes a maximum power point t racking (mpp t ) function to optimize its input voltage to extract the maximum possible power from a photovoltaic cell. it include s configurability for termination voltage, charge current and a host of other variables to allow optimum charging conditions for a wide range of li - ion batteries. a 1 mhz internal switching frequency facilitates low - cost lc filter combinations. when the battery voltage is below 3.0 volts, the device will enter a pre - charge state and apply a small, programmable charge current to safely charge the battery to a level for which full charge current can be applied. once the full charge mode has been initiated , the device will maximize available charge current to the battery by adjusting its duty cycle to regulate its input voltage to the maximum power point ( mpp ) voltage of the photovoltaic cell. if sufficient current is available from the pv cell to exceed th e safe 1c charge rate of the battery, then the programmable 1c current limit function will take precedence over the mpp control function and the pv cell voltage will rise above the mpp value. when the battery voltage has increased enough to go into mainte nance mode, the pwm control loop will force a const ant voltage across the battery. once in constant voltage mode, current is monitored to determine whe n the battery is fully charged. this regulation voltage as well as the 1c charging current can be set t o change based on battery temperature. there are 4 temperature ranges where these can be set independently, 0 - 10c, 10 - 45c, 45 - 50c and 50 - 60c. the 0c and 60c thresholds will stop charging and have 10 degrees of hysteresis. the intermediate points h ave 1 degree of hysteresis. internal protection details internal current limit the current through the inductor is sensed on a cycle by cycle basis and if current limit is reached, it will abbreviate the cycle. current limit is always active when the regulator is enabled. thermal shutdown if the temperature of the die exceeds 170 c (typical), the sw outputs will tri - state to protect the device from damage. the nflt and all other protection circuitry will stay active to inform the system of the fail ure mode. once the device cools to 160 c (typical), the device will attempt to start up again. if the device reaches 170 c, the shutdown/restart sequence will repeat. vin under - voltage lockout the device is held in the off state until vin reaches 3. 15 v . there is a 200mv hysteresis on this input, which requires the input to fall below 2.95 v before the device will disable. battery over - voltage protection the ts520 0 1 has a battery protection circuit designed to shutdown the charging profile if the battery voltage is greater than the termination voltage. the termination voltage can change based on user programming, so the protection threshold is set t o 2% above the termination voltage. shutting down the charging profile puts the ts52 0 01 in a faul t condition. fault handling nflt pin functionality in the event of a battery over - voltage, the battery temperature being outside of the safe charging range or the full charge timer expiring, charging will stop, and the nflt pin will be pulled low. when the fault condition is no longer present, the device will enter the initialize state, but the nflt pin will remain low until register 0 is read. when the register 0 is read, the nflt pin will go high until a new fault is detected. other faults when a n open thermisto r, thermal shut down, vin under - voltage, or top off time - out are detected, charging will immediately stop and the corresponding bit in register 0 will be set. the device will enter the initialize state until the fault is no l onger detected .
- 9 - ts 52001 version 1. 3 specifications subject to change www.triunesystems.com copyright ? 201 1 , triune systems, llc serial interface the ts52 0 01 features an i 2 c slave interface which offers advanced control and diagnostic features. i 2 c operation offers configuration control for termination voltages, charge current s , and charge timeouts. this configurability allow s for optimum charging conditions in a wide range of li - ion batteries. i 2 c operation also offers fault and warning indicators. whenever a fault is detected, the associated status bit in the status register is set and the nflt pin is pulled low. whenever a warning is detected, the associated status bit in the status register is set, but the nflt pin is not pulled low. reading of the status register resets the fault and warning status bits , and the nflt pin is released after all fault status bits have bee n reset. i 2 c subaddress definition figure 3 : sub - address in i 2 c transmission i 2 c bus operation the ts520 0 1 has a slave i 2 c interface that supports standard and fast mode data rates , auto - sequencing, and is compliant to i 2 c standard version 3.0. i 2 c is a two - wire serial interface where the two lines are serial clock (scl) and serial data (sda). sda must be connected to a positive supply through an external pull - up resistor. the devices communicating on this bus can drive the sda line low or rele ase it to high impedance. the device that initiates the i 2 c transaction becomes the master of the bus. communication is initiated by the master sending a start condition, a high - to - low transition on sda, while the scl line is high. after the start condi tion, the device address byte is sent, most significant bit (msb) first, including the data direction bit (r/nw). after receiving the valid address byte, the device responds with an acknowledge (ack). an ack is a low on sda during the high of the ack rel ated clock pulse. on the i 2 c bus, during each clock pulse only one data bit is transferred. the data on the sda line must remain stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as sta rt or stop c ontrol commands. a low - to - high transition on sda while the scl input is high, indicates a stop condition and is sent by the master (see figure 4 ). any number of data bytes can be transferred from the transmitter to receiver between the start and the stop conditions. each byte of eight bits is followed by one ack bit. the sda line must be released by the transmitter before the receiver can send an ack bit. the receiver that acknowledges must pull down the sda line during the ack clock pulse, so that the sda line is stable low during the high pulse of the ack - related clock period. when a slave receiver is addressed, it must generate an ack after each byte is received. similarly, the master must generate an ack after each byte that it receives from the sla ve transmitter. to ensure proper operation, setup and hold times must be met. an end of data is signaled by the master receiver to the slave transmitter by not generating an acknowledge after the last byte has been clocked out of the slave. this is done by the master receiver by holding the sda line high. the transmitter must then release the data line to enable the master to generate a st op condition.
- 1 0 - ts 52001 version 1. 3 specifications subject to change www.triunesystems.com copyright ? 201 1 , triune systems, llc figure 4 : i 2 c start / stop protocol figure 5 : i 2 c data transmission timing
- 11 - ts 52001 version 1. 3 specifications subject to change www.triunesystems.com copyright ? 201 1 , triune systems, llc charging state diagram initialize waiting for valid charging conditions no pre charge mppt w/pre charge current limit vbat > precharge t hreshold yes no 1c charging mppt w/1c current limit and full charge timer yes no faults & vbat < restart vbat < precharge threshold v bat = vterm & icharge < ieoc yes no yes no end of charge vbat regulated to termination voltage with eoc timer vbat = vterm no yes icharge < top o ff end current no en yes
- 12 - ts 52001 version 1. 3 specifications subject to change www.triunesystems.com copyright ? 201 1 , triune systems, llc register description (device address = 0x48) register address (hex) name default description 0 00 status 0x00 status bit register 1 n/a n/a n/a register not implemented 2 02 config1 (1) eeprom configuration register 3 03 config2 (1) eeprom configuration register 4 04 config3 (1) eeprom configuration register 5 05 config4 (1) eeprom configuration register 6 06 config5 (1) ee prom configuration register 7 - 16 n/a n/a n/a registers not implemented 17 11 config_enable 0x00 enable configuration register access 18 12 eeprom_ctrl (1) 0x00 eeprom control register (1) config and eeprom_ctrl registers are only accessible when config_enab le register is written. status register (status) address C 0x00h data bit d7 d6 d5 d4 d3 d2 d1 d0 field name batt_ov 1c_to temp_0c temp_60c tsd top_to vin_uv th_open read/write r r r r r r r r field name bit definition (2 ) batt_ov battery over - volta ge 1c_to full charge timer has timed out temp_0c thermistor indicates battery temperature < 0 c temp_60c thermistor indicates battery temperature > 60 c tsd thermal shutdown top_to top off timer has timed out vin_uv vin under - voltage th_open thermis tor open (battery not present ) (1) faults are defined as batt_ov, 1c_to, temp_0c, and temp_60c. warnings are defined as tsd, top_to, vin_uv, and th_open. faults cause the nflt pin to be pulled low, warnings do not cause the nflt pin to be pulled low. all s tatus bits are cleared after register read access. nflt pin will go high impedance (open drain output) after the status register has been read and all status bits have been reset.
- 13 - ts 52001 version 1. 3 specifications subject to change www.triunesystems.com copyright ? 201 1 , triune systems, llc configuration register (config1) address C 0x02h data bit d7 d6 d5 d4 d3 d2 d1 d0 field name pre_chrg[1:0] v_term_0_10[2:0] v_term_10_45[2:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w field name bit definition pre_chrg[1:0] (1) pre - charging configuration 00 C C C C (2) voltage termination 0 - 10 c configuration 000 C C C C C C C C (2) voltage termination 10 - 45 c configuration 000 C C C C C C C C pre_chrg note : maximum output current when v bat < 3.0 v. (2) v_term note: unique settings available for battery temperatures 0 - 10 c , 10 - 45 c , 45 - 50 c , and 50 - 60 c . for <0 c and >60 c , charging is disabled and a fault is set.
- 14 - ts 52001 version 1. 3 specifications subject to change www.triunesystems.com copyright ? 201 1 , triune systems, llc configuration register (config2) address C 0x03h data bit d7 d6 d5 d4 d3 d2 d1 d0 field name eoc[1:0] v_term_45_50[2:0] v_term_50_60[2:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w field name bit definition eoc [1:0] (1) end of charge configuration 00 C C C C (2) voltage termination 45 - 5 0 c configuration 000 C C C C C C C C (2) voltage termination 50 - 60 c configuration 000 C C C C C C C C eoc note: maximum output current when v bat < 3.0 v. (2) v_term note: uni que settings available for battery temperatures 0 - 10 c , 10 - 45 c , 45 - 50 c , and 50 - 60 c . for <0 c and >60 c , charging is disabled and a fault is set.
- 15 - ts 52001 version 1. 3 specifications subject to change www.triunesystems.com copyright ? 201 1 , triune systems, llc configuration register (config3) address C 0x04h data bit d7 d6 d5 d4 d3 d2 d1 d0 field name max_chrg_cu rr_0_10[3:0] max_chrg_curr_10_45[3:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w field name bit definition max_chrg_curr_0_10[3:0] (1) maximum charge current 0 - 10 c configuration 0000 C C C C C C C C C C C C C C C C (1 ) maximum charge current 10 - 45 c configuration 0 000 C C C C C C C C C C C C C C C C max_chrg_curr note: unique settings available for ba ttery temperatures 0 - 10 c , 10 - 45 c , 45 - 50 c , and 50 - 60 c . for <0 c and >60 c , charging is disabled and a fault is set .
- 16 - ts 52001 version 1. 3 specifications subject to change www.triunesystems.com copyright ? 201 1 , triune systems, llc configuration register (config4) address C 0x05 h data bit d7 d6 d5 d4 d3 d2 d1 d0 field name max_chrg_curr_45_50[3:0] max_chrg_curr_5 0_60[3:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w field name bit definition max_chrg_curr_45_50[3:0] (1) maximum charge current 45 - 50 c configuration 0000 C C C C C C C C C C C C C C C C (1) maximum charge current 50 - 60 c configuration 0000 C C C C C C C C C C C C C C C C max_chrg_curr note: unique settings available for battery temperatures 0 - 10 c , 10 - 45 c , 45 - 50 c , and 50 - 60 c . for <0 c and >60 c , charging is disabled and a fault is set.
- 17 - ts 52001 version 1. 3 specifications subject to change www.triunesystems.com copyright ? 201 1 , triune systems, llc configuration register (config5) address C 0x06h data bit d7 d6 d5 d4 d3 d2 d1 d0 field name top_end th top_to[2:0] 1c_to[2:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w field name bit definition top_end (1) top off end configuration 0 C C ( 2 ) thermistor configuration 0 C C (3) top off timer time out configuration 000 C C C C C C C C (4) full charge timer time out configuration 000 C C C C C C C C top_end note: charging stops when v bat = v termination and i bat < top off end . (2) th note: setting for nominal thermistor and reference resistor value. (3) top_to note: timer starts when v bat = v term ination and i bat < eoc. (4) 1c_to note: timer starts when v bat > 3.0v.
- 18 - ts 52001 version 1. 3 specifications subject to change www.triunesystems.com copyright ? 201 1 , triune systems, llc enable configuration register (config_enable) address C 0x11 h data bit d7 d6 d5 d4 d3 d2 d1 d0 field name not used not used not used not used not used not used not used en _cfg read/writ e r r r r r r r r/w reset value 0 0 0 0 0 0 0 0 field name bit definition en _cfg enable access control bit for configuration registers 2 - 6 0 C C eeprom control register (eeprom_ctrl) address C 0x12h data bit d7 d6 d5 d4 d3 d2 d1 d0 field name not used not used not used not used not used not used not used ee_prog read/write r r r r r r r r/w reset value 0 0 0 0 0 0 0 0 field name bit definition ee_prog (1) eeprom program control bit for configuration registers 2 - 6 0 C C ee_prog note : inputs vin and en must be present for 200 ms. external component s election the internal compensation is optimized for a 4.7uf output capacitor and a 4.7uh inductor. to keep the output ripple low, a low esr (less than 35mohm) ceramic is recommended.
- 19 - ts 52001 version 1. 3 specifications subject to change www.triunesystems.com copyright ? 201 1 , triune systems, llc package mechanical d rawings
- 20 - ts 52001 version 1. 3 specifications subject to change www.triunesystems.com copyright ? 201 1 , triune systems, llc application using a multi - layer pcb to maximize the efficiency of this package for applicati on on a single layer or multi - layer pcb, certain guidelines must be followed when laying out this part on the pcb. the following are guidelines for mounting the exposed pad ic on a multi - layer pcb with ground a plane . jedec standard fr4 pcb cross - secti on: multi - layer board (cross - sectional view) in a multi - layer board application, the thermal vias are the primary method of heat transfer from the package thermal pad to the internal ground plane. the efficiency of this method depends on several factors , including die area, number of thermal vias, thickness of copper, etc. package thermal pad solder pad (land pattern) thermal via's package outline package and pcb land configuration for a multi-layer pcb ( square ) package solder pad package solder pad ( bottom trace ) thermal via component traces thermal isolation power plane only 1 . 5748 mm 0 . 0 - 0 . 071 mm board base & bottom pad 0 . 5246 - 0 . 5606 mm power plane ( 1 oz cu ) 1 . 0142 - 1 . 0502 mm ground plane ( 1 oz cu ) 1 . 5038 - 1 . 5748 mm component trace ( 2 oz cu ) 2 plane 4 plane
- 21 - ts 52001 version 1. 3 specifications subject to change www.triunesystems.com copyright ? 201 1 , triune systems, llc the above drawing is a representation of how the heat can be conducted away from the die using an exposed pad package. each application will have different requ irements and limitations and therefore the user should use sufficient copper to dissipate the power in the system. the output current rating for the linear regulators may have to be de - rated for ambient temperatures above 85c. the de - rate value will depen d on calculated worst case power dissipation and the thermal management implementation in the application. application using a single layer pcb layout recommendations for a single layer pcb: utilize as much copper area for power management. in a sing le layer board application the thermal pad is attached to a heat spreader (copper areas) by using low thermal impedance attachment method (solder paste or thermal conductive epoxy). in both of the methods mentioned above it is advisable to use as much cop per traces as possible to dissipate the heat. important: if the attachment method is not implemented correctly, the functionality of the product is not guaranteed. power dissipation capability will be adversely affected if the device is incorrectly mount ed onto the circuit board. mold compound die epoxy die attach exposed pad solder thermal vias with cu plating single layer , 2 oz cu ground layer , 1 oz cu signal layer , 1 oz cu bottom layer , 2 oz cu 20 % cu coverage 90 % cu coverage 5 % - 10 % cu coverage note : not to scale use as much copper area as possible for heat spread package thermal pad package outline
- 22 - ts 52001 version 1. 3 specifications subject to change www.triunesystems.com copyright ? 201 1 , triune systems, llc legal notices information contained in this publication regarding device applications and the like is provided only for your convenience an d may be superseded by updates. it is your responsibility to ensure that your applica tion meets with your specifications. typical parameters which may be provided in triune systems data sheets and/or specifications can and do vary in different applications and actual performance may vary over time . all operating parameters, including typicals must be validated for your application by your technical experts. triune systems makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but no t limited to its condition, quality, performance, merchantability or fitness for purpose. triune systems disclaims all liability arising from this information and its use. triune system products are not des igned, intended, or authorized for use as componen ts in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the triune systems product could create a situation where personal injury or de ath ma y occur. should the buyer purchase or use triune systems products for any such unintended or unauthorized application, the buyer shall indemnify and hold triune systems, and its officers, employees, subsidiaries, affiliates, and distributors harmless again st all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unautho rized use, even if such claim alleges that triune systems was negligent regarding the design or manufacture of the part. no licenses are conveyed, implicitly or otherwise, under any triune systems intellectual property rights. trademarks the triune systems? name and logo, mppt - lite?, and nanosmart? are trademarks of triune systems, llc. in the u.s.a.. all other trademarks mentioned herein are property of their respective companies. ? 2012 triune systems, llc. all rights reserved.

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